`include "PRV564Config.v"
`include "PRV564Define.v"
`timescale 1ns/1ps
/*****************************************************************************************
 *    author : Jack's Team
 *    e-mail : 
 *    date   : 20210726
 *    desc   : PRV564 second version test bench （564二期测试框架）
 *    version: 0000 (Orignal version)

**********************************************************************************************/
module TestBench_RevB(

);
//-----------------Test bench global signal----------------------
    reg                 Kernel_CLKi;                                    //Kernel clock input
    reg                 Kernel_ARSTi;                                   //Kernel reset input (Async)
    reg                 INT_Mtimer,     INT_Stimer,     INT_Msoft;              //Timer and Software interrupt
    reg                 INT_Mext,       INT_Sext;                           //External interrupt
    reg                 INT_NMI;                                        //None Maskable interuupt
    reg [`XLEN-1:0]     Mtimer;
//-----------------Kernel Write Back Information-------------------
    wire                CommitValid;                                        //write back instruction is valid
    wire                wen;                                                //write back enable
    wire [`XLEN-1:0]    CommitPC,          wdata;                           //write back data
    wire [4:0]          wdest;                                              //write back to regfile index
    wire [1:0]          priviledgeMode;                                     //write back instruction's privlage
//--------------------CSR information------------------------------
    wire [`XLEN:0]      mstatus;
    wire [`XLEN:0]      sstatus;
    wire [`XLEN:0]      mepc;
    wire [`XLEN:0]      sepc;
    wire [`XLEN:0]      mtval;
    wire [`XLEN:0]      stval;
    wire [`XLEN:0]      mtvec;
    wire [`XLEN:0]      stvec;
    wire [`XLEN:0]      mcause;
    wire [`XLEN:0]      scause;
    wire [`XLEN:0]      satp;
    wire [`XLEN:0]      mip;
    wire [`XLEN:0]      mie;
    wire [`XLEN:0]      mscratch;
    wire [`XLEN:0]      sscratch;
    wire [`XLEN:0]      mideleg;
    wire [`XLEN:0]      medeleg;
//-----------------FIB bus ---------------------------------------
/*
    wire                FIB0_WRENo, FIB1_WRENo;        //write to FIB1 enable
    wire                FIB0_REQo,  FIB1_REQo;        //request FIB1 trans
    wire                FIB0_ACKi,  FIB1_ACKi;         //request acknowledge
    wire                FIB0_FULLi, FIB1_FULLi;        //FIB1 FIFO full
    wire [7:0]          FIB0_IDo,   FIB1_IDo;
    wire [7:0]          FIB0_CMDo,  FIB1_CMDo;
    wire [3:0]          FIB0_BURSTo,FIB1_BURSTo;
    wire [3:0]          FIB0_SIZEo, FIB1_SIZEo;
    wire [`XLEN-1:0]    FIB0_ADDRo, FIB1_ADDRo;      
    wire [`XLEN-1:0]    FIB0_DATAo, FIB1_DATAo;
    wire [7:0]          FIB0_IDi,   FIB1_IDi;
    wire [7:0]          FIB0_RPLi,  FIB1_RPLi;
    wire                FIB0_Vi,    FIB1_Vi;
    wire [`XLEN-1:0]    FIB0_DATAi, FIB1_DATAi;
*/
//-------------------Cache port-------------------------------------
    wire                 ICache_AQ_V,      DCache_AQ_V;
    wire [7:0]           ICache_AQ_ID,     DCache_AQ_ID;
    wire [7:0]           ICache_AQ_CMD,    DCache_AQ_CMD;
    wire                 ICache_AQ_CI,     DCache_AQ_CI;
    wire                 ICache_AQ_WT,     DCache_AQ_WT;
    wire [15:0]          ICache_AQ_BSEL,   DCache_AQ_BSEL;
    wire [127:0]                           DCache_AQ_WDATA;
    wire [`XLEN-1:0]     ICache_AQ_ADDR,   DCache_AQ_ADDR;
    wire                 ICache_AQ_FULL,   DCache_AQ_FULL;
    wire                 ICache_RQ_V,      DCache_RQ_V;
    wire [7:0]           ICache_RQ_ID,     DCache_RQ_ID;
    wire                 ICache_RQ_WRERR,  DCache_RQ_WRERR;
    wire                 ICache_RQ_RDERR,  DCache_RQ_RDERR;
    wire                 ICache_RQ_RDY,    DCache_RQ_RDY;
    wire [127:0]         ICache_RQ_RDATA,  DCache_RQ_RDATA;
    wire                 ICache_RQ_ACK,    DCache_RQ_ACK;

initial begin
    $dumpfile("tb.lxt");
    $dumpvars(0,PRV564_Kernel);
    Kernel_CLKi = 1'b1;
    Kernel_ARSTi= 1'b1;
    INT_Mtimer  = 1'b0;
    INT_Stimer  = 1'b0;
    INT_Msoft   = 1'b0;
    INT_Mext    = 1'b0;
    INT_Sext    = 1'b0;
#10
    Kernel_ARSTi= 1'b0;
    $display("Ignition emission!");
#1000
    $finish;
end
always begin
#10
    Kernel_CLKi = ~Kernel_CLKi;
    Mtimer      = Mtimer + 1;
end
//-------------------打印写回信息--------------------
always@(negedge Kernel_CLKi)begin
    if(CommitValid)begin
        if(wen)begin
            $display("Write back PC = %h, GPR Index = %h, Data = %h, Privilege = %h", CommitPC, wdest, wdata, priviledgeMode);
        end
        else begin
             $display("Write back PC = %h, Privilege = %h", CommitPC, priviledgeMode);
        end
    end
    else begin
        $display("No write back in current cycle");
    end
end
    
PRV564_Kernel       PRV564_Kernel
(
    .Kernel_CLKi            (Kernel_CLKi),
    .Kernel_ARSTi           (Kernel_ARSTi),
//---------------TLB Access port---------------------------
    .ITLB_FIBo_WREN         (),
    .ITLB_FIBo_REQ          (),
    .ITLB_FIBi_ACK          (),
    .ITLB_FIBi_FULL         (),
    .ITLB_FIBo_ID           (),
    .ITLB_FIBo_CMD          (),
    .ITLB_FIBo_BURST        (),
    .ITLB_FIBo_SIZE         (),
    .ITLB_FIBo_ADDR         (),
    .ITLB_FIBo_DATA         (),
    .ITLB_FIBi_ID           (),
    .ITLB_FIBi_RPL          (),
    .ITLB_FIBi_V            (),
    .ITLB_FIBi_DATA         (),
    //---------------FIB0-----------------
    .DTLB_FIBo_WREN         (),
    .DTLB_FIBo_REQ          (),
    .DTLB_FIBi_ACK          (),
    .DTLB_FIBi_FULL         (),
    .DTLB_FIBo_ID           (),
    .DTLB_FIBo_CMD          (),
    .DTLB_FIBo_BURST        (),
    .DTLB_FIBo_SIZE         (),
    .DTLB_FIBo_ADDR         (),
    .DTLB_FIBo_DATA         (),
    .DTLB_FIBi_ID           (),
    .DTLB_FIBi_RPL          (),
    .DTLB_FIBi_V            (),
    .DTLB_FIBi_DATA         (),
//----------------To cache port---------------------------
    .ICache_AQ_V            (ICache_AQ_V),      
    .DCache_AQ_V            (DCache_AQ_V),
    .ICache_AQ_ID           (ICache_AQ_ID),     
    .DCache_AQ_ID           (DCache_AQ_ID),
    .ICache_AQ_CMD          (ICache_AQ_CMD),    
    .DCache_AQ_CMD          (DCache_AQ_CMD),
    .ICache_AQ_CI           (ICache_AQ_CI),     
    .DCache_AQ_CI           (DCache_AQ_CI),
    .ICache_AQ_WT           (ICache_AQ_WT),     
    .DCache_AQ_WT           (DCache_AQ_WT),
    .ICache_AQ_BSEL         (ICache_AQ_BSEL),   
    .DCache_AQ_BSEL         (DCache_AQ_BSEL),
    .DCache_AQ_WDATA        (DCache_AQ_WDATA),
    .ICache_AQ_ADDR         (ICache_AQ_ADDR),   
    .DCache_AQ_ADDR         (DCache_AQ_ADDR),
    .ICache_AQ_FULL         (ICache_AQ_FULL),   
    .DCache_AQ_FULL         (DCache_AQ_FULL),
    .ICache_RQ_V            (ICache_RQ_V),  
    .DCache_RQ_V            (DCache_RQ_V),
    .ICache_RQ_ID           (ICache_RQ_ID),  
    .DCache_RQ_ID           (DCache_RQ_ID),
    .ICache_RQ_WRERR        (ICache_RQ_WRERR),  
    .DCache_RQ_WRERR        (DCache_RQ_WRERR),
    .ICache_RQ_RDERR        (ICache_RQ_RDERR),  
    .DCache_RQ_RDERR        (DCache_RQ_RDERR),
    .ICache_RQ_RDY          (ICache_RQ_RDY),  
    .DCache_RQ_RDY          (DCache_RQ_RDY),
    .ICache_RQ_RDATA        (ICache_RQ_RDATA),  
    .DCache_RQ_RDATA        (DCache_RQ_RDATA),
    .ICache_RQ_ACK          (ICache_RQ_ACK),  
    .DCache_RQ_ACK          (DCache_RQ_ACK),  

//---------------Interrupt signal-------------------------
    .Kernel_MTIi            (INT_Mtimer),
    .Kernel_MSIi            (INT_Msoft),
    .Kernel_MEIi            (INT_Mext),
    .Kernel_SEIi            (INT_Sext),
    .Kernel_NMIPLi          (1'b0),
    .Kernel_NMIEEi          (1'b0),
    .Kernel_NMIGi           (INT_NMI),
//--------------YSYX210152_Machine mode timer-----------------------
    .Kernel_MTIMEi          (Mtimer),
    .InstrPC                (CommitPC),
    //output [31:0]InstrCommit,
    .IntRegState            (),
    //.ArchEvent(ArchEvent),
    //.TrapEvent(TrapEvent),
    .CommitValid            (CommitValid),
    .skip                   (),
    .isRVC                  (),
    .scFailed               (),
    .wen                    (wen),
    .wdest                  (wdest),
    .wdata                  (wdata),

    //CSR output for difftest
    .priviledgeMode         (priviledgeMode),
    .mstatus                (mstatus),
    .sstatus                (sstatus),
    .mepc                   (mepc),
    .sepc                   (sepc),
    .mtval                  (mtval),
    .stval                  (stval),
    .mtvec                  (mtvec),
    .stvec                  (stvec),
    .mcause                 (mcause),
    .scause                 (scause),
    .satp                   (satp),
    .mip                    (mip),
    .mie                    (mie),
    .mscratch               (mscratch),
    .sscratch               (sscratch),
    .mideleg                (mideleg),
    .medeleg                (medeleg)
);
//------------------------Virtual-Cache access-------------------------
AQRQ_TCM            
#(.INIT_FILE        ("InitialData.txt"))
TCM(
    .ICache_AQ_V            (ICache_AQ_V),      
    .DCache_AQ_V            (DCache_AQ_V),
    .ICache_AQ_ID           (ICache_AQ_ID),     
    .DCache_AQ_ID           (DCache_AQ_ID),
    .ICache_AQ_CMD          (ICache_AQ_CMD),    
    .DCache_AQ_CMD          (DCache_AQ_CMD),
    .ICache_AQ_CI           (ICache_AQ_CI),     
    .DCache_AQ_CI           (DCache_AQ_CI),
    .ICache_AQ_WT           (ICache_AQ_WT),     
    .DCache_AQ_WT           (DCache_AQ_WT),
    .ICache_AQ_BSEL         (ICache_AQ_BSEL),   
    .DCache_AQ_BSEL         (DCache_AQ_BSEL),
    .DCache_AQ_WDATA        (DCache_AQ_WDATA),
    .ICache_AQ_ADDR         (ICache_AQ_ADDR),   
    .DCache_AQ_ADDR         (DCache_AQ_ADDR),
    .ICache_AQ_FULL         (ICache_AQ_FULL),   
    .DCache_AQ_FULL         (DCache_AQ_FULL),
    .ICache_RQ_V            (ICache_RQ_V),  
    .DCache_RQ_V            (DCache_RQ_V),
    .ICache_RQ_ID           (ICache_RQ_ID),  
    .DCache_RQ_ID           (DCache_RQ_ID),
    .ICache_RQ_WRERR        (ICache_RQ_WRERR),  
    .DCache_RQ_WRERR        (DCache_RQ_WRERR),
    .ICache_RQ_RDERR        (ICache_RQ_RDERR),  
    .DCache_RQ_RDERR        (DCache_RQ_RDERR),
    .ICache_RQ_RDY          (ICache_RQ_RDY),  
    .DCache_RQ_RDY          (DCache_RQ_RDY),
    .ICache_RQ_RDATA        (ICache_RQ_RDATA),  
    .DCache_RQ_RDATA        (DCache_RQ_RDATA),
    .ICache_RQ_ACK          (ICache_RQ_ACK),  
    .DCache_RQ_ACK          (DCache_RQ_ACK),  
    .GLBi_CLK               (Kernel_CLKi)
);
endmodule